cse 401 : Computer Architecture : Winter 2019
Professor Ernesto Gomez
phone: (909) 537-5429
office hours: TBA
Student assistant: Christopher Casillas firstname.lastname@example.org
TTh 2:00-3:50 JB-109, Lab TTh 4:00-5:20 JB-359
Lab reports should include Verilog source code, and verification that it works such as screenshots of Vivado graphic display or other output.
Should be turned in electronically by email with copy to both email@example.com and firstname.lastname@example.org.
All emails should have CSE401 and name of assignment in the subject line.
If you are working with another person, both your names should be indicated in the email.
FINAL: Friday 2-4 in JB-109
For those who have notified me that you can not make the Friday final (due to work, travel, conflict with
MAKEUP final: Wednesday 2-4 in JB 358
IMPORTANT LAB NOTE: It turns out that the output from the ALU marked "zero" is not actually zero - it is a bit that is
set in jump instructions that says "we are taken the jump" - this is combined with the control bit from the opcode that
says it is a jump, and when both are 1 it sets the mux in Lab1 to choose the jump address. Here's what the code in alu.v
looks like: it is inside the always block
if (A==0 ) zero <= 1 ;
else zero <= 0 ;
with thanks to Samuel Jacuinde, who noticed this and brought it to my attention.
Lab Source Files and Notes
Vivado info and tutorials from Xilinix
If you want ISE istructions, Google search on "xilinix verilog tutorial" brings up lots of stuff with ISE
Verilog videos thanks to Dr. Yu
Helpful Verilog Tutorial from Asic-World uses Icarus
XILINX download -
Download the free webpack, not the demo system.
Icarus Verilog is a free alternative to XILINIX, is less powerful but works on Linux and IOS as well as Windows
To run the Icarus compiler in the labs - compile command is "iverilog" (usage is similar to gcc/g++, see "man iverilog"
The icarus runtime system (to run and link multiple separate modules) is "vvc", see "man vvc"
Getting xilinx to work with windows 8 or later Thanks to Takenori Tsuruga, who did this in our lab.
Icarus and GTKwave viewer
getting started with Icarus
Vivado reference manuals
Sample memory file
Handy MIPS instruction reference at U. of Idaho:
Also MIPS opcodes
ANNOUNCEMENTS: (note - all test dates are subject to change, except final)
Will not be in today may 13 - my cold got worse. Start reading first half of Ch 4. Pay particular attention
to pipeline design and performance. Will discuss on Wendesday
MIDTERM - May 8, in class, chapters 1-3. You are allowed 1.5 pages of notes (3 sides total),
calculator and the MIPS reference card.
The file mem.v - memory for lab1 - has been added to the link "lab source files anTd notes", in "source" subdirectory, see above.
GRADING: HW 10%, Labs 30%, Midterm 20%, Final 40%. Labs may be done in groups of 2, all other work is individual.
You are allowed 2 pages of notes (both sides), calculator and the MIPS referene card:
With thanks to Michael Mar: MIPS reference card pdf
All homework and labs will be turned in via email to email@example.com.
All work except the final must be turned in on or before the last day of the term.
All emails should have CSE 401 in the subject line.
FINAL -(Probably) Ch 1,2,3,4 and 5. You are allowed 3 pages (both sides) of notes. You may need
extra sheets of blank paper.
All homework and labs should be turned in by email - do it at the time we are
covering the corresponding material in class. There is no specific date to turn
it in, but ideally turn it in as soon as you finish it. No homework will be accepted
after the last day of the term (before finals week)
HW Chapter 1 : 1.12, extra credit 1.15
Chapter 2 : 2.4,2.27
Chapter 3 : 3.8,3.24
Chapter 4 : 4.8,4.12,4.15
Chapter 5 : 5.3,5.5.6
Problem sets are correct for 5th edition.
Extra problem - due anytime before the final:
Assume a 64 bit processor with instruction set similar to MIPS in that
the only memory instructions are LOAD and STORE to/from register, and all
other instructions are R-format (suitably extended for 64 bits). You have
64 registers and a 5 stage pipeline. L1 cache returns in 1 cycle, L2 cache
takes 4 cycles for an L1 miss. Cache is write-through handled in hardware without
CPU action, memory has a 20 cycle initial delay and after that supplies one word
per cycle, and an L2 miss has a 40 cycle cost and loads 20 words into cache.
You are asked to design a 12 core chip where each core is as described, and
will run at 2GHz. What memory bandwidth is required to support all 12 cores?
Look up current memory bus speeds - are they sufficient to our requirements? State all
1. You will need to make some assumption about the typical instruction
2. You may need to make other assumptions.
3. Not all the given information is relevant to this problem.)
All homework and labs should be should be turned in on or before the last day
of classes. If you have worked with a partner in the lab,
both of your names should be in the code or in a note submitted with it.
You may bring the MIPS instructio reference sheet (or a copy of it) in addition to
all other notes.
After I accept that your lab is working and check you off in the lab, I
still want you to send me your code by email including a screenshot.
LAB ANNOUNCEMENTS: (
Note that Lab 6 (page 32 in the lab manual) has an example program and instructions on how to load and verify that it works. Use this to test your completed pipeline.
- Extra Credit Opportunity: Forwarding Unit
- Added Lab 5 Notes and Lab 6 Notes.
- The following instructions specified in the Lab 4 Notes may be used to test the the pipeline for Lab 4.
- Lab 3 Notes
have been updated to reflect the proper instructions. There are also
new comments added in the notes to address problems that students ran
into during the lab.due on 06/15/2011 before 11:59PM.
- Lab 3 Notes have been posted.
- There will be 0.5 pts off of the lab grade for each day the lab
write-up is late up to a max of 7 days (-3.5pts off). After this
period, the lab will no longer be accepted.
- Extra Credit opportunities will be accounced during the lab
section time and will be awarded on a 0.5 pt basis. Specify your extra
credit you are requesting points towards in your lab write-up email.
- Read Lab 2 Notes for information on the Lab 2 requirements.
- The timing diagram is also included in the Lab 2 source files.
- Lab 2 required modules: REG, CONTROL, ID_EX, S_EXTEND all
instatiatied in I_DECODE, which will be instanted in PIPELINE with
CSE 401 Syllabus
Some info on memory: 1 ,
Look at "Keith on Hardware" here